<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>GT200 on Dispatch3 Inc.</title><link>https://dispatch3.com/tags/gt200/</link><description>Recent content in GT200 on Dispatch3 Inc.</description><generator>Hugo -- gohugo.io</generator><language>en-us</language><lastBuildDate>Sun, 27 May 2012 00:00:00 -0400</lastBuildDate><atom:link href="https://dispatch3.com/tags/gt200/index.xml" rel="self" type="application/rss+xml"/><item><title>GPU Hack: LLVM for pre-Fermi Kernels</title><link>https://dispatch3.com/posts/gpu_hack_pre_fermi/</link><pubDate>Sun, 27 May 2012 00:00:00 -0400</pubDate><guid>https://dispatch3.com/posts/gpu_hack_pre_fermi/</guid><description>I&amp;rsquo;ve been cleaning up a set of kernels so that they will run optimally on GT200 devices (sm_1x). The kernels run extremely well on Fermi so I was disappointed when the opencc compiler struggled to use a reasonable number of registers despite having access to the same number of registers per thread.
I was getting over 200 bytes of spills in a critical kernel that had no spills at all on Fermi.</description></item></channel></rss>